Method of extracting a semiconductor device compact model

ABSTRACT

This invention is a method of extracting a semiconductor device compact model by using knowledge of the equations used inside the compact model. Starting by fitting a small subset of the model parameters, the remaining model parameters are fitted and as each new subset of model parameters are fitted, the previously fitted model parameters are adjusted to compensate for the changes introduced due to the currently optimized parameters. This invention details the method of making these adjustments.

TECHNICAL FIELD OF THE INVENTION

This invention relates generally to electronic testing and characterizing of semiconductor IC processes. More specifically it relates to extraction of compact model parameters from semiconductor device measurement data.

BACKGROUND ART

In U.S. Pat. No. 6,779,157 Kondo et al. outline a method use a simulation model to simulate in and calculate local processes that occur during device fabrication and uses the resulting electrical behavior as data to extract BSIM3 model parameters. So the invention is to use the results of simulating a semiconductor device as if it were real data.

In U.S. Pat. No. 6,560,568 Singhal et al. outline a method wherein the results of multiple measurements are itemized in a matrix and the standard deviation is obtained and then the electrical parameters are obtained after normalizing the columns to have a mean of zero and a variance of one.

In U.S. Pat. No. 6,397,172 Gurney et al. outline a method wherein the simulation model is regenerated as required based on the effective simulation conditions and if necessary relevant measurement data relevant to the effective operating conditions are used in regenerating the model. The method also allows selecting a model based on the effective simulation conditions.

In U.S. Pat. No. 6,314,390 Bittner et al. outline a method of obtaining vectors of model parameters from measured data and applying genetic operators and meta evolution operators to create a new population of vectors from which vectors of best fitness are selected.

In a publication entitled “Pre-Silicon Parameter Generation Methodology Using BSIM3 for Circuit Performance-Oriented Device Optimization”, IEEE Transactions on Semiconductor Manufacturing, Vol. 14, No. 2, May 2001, Miyama et al. outline a method to extract BSIM3 model parameters before device fabrication. The method is to start with a subset of the BSIM3 parameters considered to be critical and to divide that set into two types namely those which change from generation to generation and those that remain the same. Some of these critical parameters are calculated and some are extracted from data so that finally BSIM3 model parameters are obtained before device fabrication.

SUMMARY OF THE INVENTION

There are more than 60 parameters in the BSIM3 model and they cannot all be optimized at the same time. Yet the correct value of many of these parameters depends upon the value of other parameters. So at any point in the optimization sequence you will have a set K of parameters which have been optimized and a set P whose values are yet to be determined. So in this suggested extraction method, parameters from the set K will have to be corrected when parameters from the set P are being optimized. The following is an example. $\begin{matrix} {V_{th} = {V_{{th}\quad 0} - {{D_{{VT}\quad 0}\left\lbrack {{\mathbb{e}}^{A} + {2{\mathbb{e}}^{2A}}} \right\rbrack}\left( {V_{bi} - \phi_{s}} \right)}}} & (1) \\ {A = {{- D_{{VT}\quad 1}}\frac{L_{eff}}{2l_{t}}}} & (2) \end{matrix}$

Consider the case of the threshold voltage V_(th) using the gate characteristic at a V_(ds) of 50 mV and zero back bias. When V_(th0) is set using the long channel gate characteristic, D_(VT0) and D_(VT1) are unknown. So a value of V_(th0) is set using D_(VT0)=0. Then when you optimize either D_(VT0) or D_(VT1), at each iteration you must first increase V_(th0) from it's original optimized value by the amount C given by equations 3, 4 where L_(effLC) is the long channel effective gate lenth, because otherwise the long channel V_(th) is affected. This correction will not affect the stability of the Levenburg-Marquardt algorithm. $\begin{matrix} {C = {{D_{{VT}\quad 0}\left\lbrack {{\mathbb{e}}^{D} + {2{\mathbb{e}}^{2D}}} \right\rbrack}\left( {V_{bi} - \phi_{s}} \right)}} & (3) \\ {D = {{- D_{{VT}\quad 1}}\frac{L_{effLC}}{2l_{t}}}} & (4) \end{matrix}$

BEST MODE FOR CARRYING OUT THE INVENTION

In order to accurately and repeatably extract the BSIM3 model, it is important to compute some of the parameters by solving the model equations using the intermediate variables used inside the model. Obtaining the mobility parameters is done this way as shown below.

In the absence of back-bias all three mobility models in the BSIM3 model have the form of equation 5 where the most often used P is the equation 6. We use three data points from F_(j)G₀B₀T_(n) at V_(gs)=2×V_(th), V_(gs)=0.5×(V_(dd)+2×V_(th)) and V_(gs)=V_(dd) because the current and electric field are sufficiently low as to avoid the effects of source/drain resistance and mobility degradation.

These 3 points are known to be in the linear region. The effective mobilities μ_(eff) _(—) ₁, μ_(eff) _(—) ₂ & μ_(eff) _(—) ₃ needed at the 3 points points are obtained directly from the model by overriding the intermediate variable μ_(eff) inside the model code incrementally until the required I_(d) is obtained. In this patent application overriding means to substitute your estimated value in place of the value 9 the intermediate variable would otherwise have had. Then you will have the 3 values μ_(eff) _(—) ₁, μ_(eff) _(—) ₂ & μ_(eff) _(—) ₃ and 3 equations of the form of equation 5 at the 3 values P₁, P₂ & P₃, which are solved by matrix inversion to obtain μ₀, μ_(a) and μ_(b). $\begin{matrix} {{\frac{\mu_{0}}{\mu_{eff\_ n}} - {P_{n} \cdot U_{a}} - {P_{n}^{2} \cdot U_{b}}} = 1} & (5) \\ {P_{n} = \frac{V_{gsteff} + {2V_{th}}}{T_{ox}}} & (6) \end{matrix}$

There are 16 optimization steps in this extraction method. As the parameters are computed in each step, they are set at that value for the following steps. Since the LMA allows a parameter to adjust the significance of each data point, one can use a significance of the drain current at each data point divided by the smallest drain current of the data set. This will allow all data points to be optimized equally. This is done in every LMA iteration.

The first step is to calculate the effective threshold voltage of the 5 MOSFETs from the 15 gate characteristics at minimum V_(ds) which is obtained from the max slope n and the I_(m) and V_(gs) at that point in the gate characteristic as $\begin{matrix} {V_{th} = {V_{gs} - \frac{I_{m}}{m} - \frac{V_{ds}}{2}}} & (7) \end{matrix}$

Set the parameter V_(th0) to the V_(th) obtained for the FET #0 from the curve F₀G₀B₀T₀.

Now we initialize several parameters to their starting values. The parameters set to zero are U_(a), U_(b), U_(c), P_(rwg), P_(dibl1), P_(diblb), C_(dsc), C_(dscd), C_(dscb), N_(lx), D_(VT0), D_(VT1), D_(VT2), K_(3b), D_(VT0w), Eta₀, Eta_(b), A_(gs), B₀, B₁, N_(gate), K₂, A₁, D_(VT2w), D_(VT0w), C_(it). V_(off) and N_(factor). T_(oxm) is set to the oxide thickness, μ=0.1, R_(dsw)=200, W_(r)=1, V_(sat)=150000, P_(vag)=0.1, P_(clm)=0.3, P_(dibl2)=0.2, D_(rout)=100, P_(scbe1)=4.24×10¹⁰, P_(scbe2)=1×10⁻⁵, K₃=−2.6, W₀=1×10⁻⁷, D_(VT1w)=1, D_(sub)=1, K_(eta)=−0.047, Delta=0.01, K₁=0.5, A₂=1 and V_(bm)=−1.1×V_(dd).

Now using the drain currents I_(j) of the j^(th) FET at the highest V_(gs) point on the curves F₀G₀B₀T₀, F₁G₀B₀T₀, F₂G₀B₀T₀, F₃G₀B₀T₀, you calculate L_(int) and W_(ift) as follows. Increment W_(ift) from it's minimum expected value to it's maximum expected value in an outer loop in increments of a few nm, and increment L_(int) from it's minimum expected value to it's maximum expected value in an inner loop in increments of a few nm and compute the error for each j^(th) FET as compared to the long-wide FET #0 as in eqn 8. $\begin{matrix} {{err} = {{1 - {\frac{I_{j} \cdot L_{effj}}{W_{effj}} \cdot \frac{W_{{eff}\quad 0}}{I_{0} \cdot L_{{eff}\quad 0}}}}}} & (8) \\ {L_{eff} = {L_{drawn} - \left( {2 \times L_{int}} \right)}} & (9) \\ {W_{eff} = {W_{drawn} - \left( {2 \times W_{int}} \right)}} & (10) \end{matrix}$

For each combination of W_(ift) and L_(int) select the worst err of the FETs #0, #1, #2 and #3, and seek the combination of W_(int) and L_(int) that yield the smallest worst err for the FETs. This is now the correct W_(int) and L_(int) that is needed.

Now we use the LMA to optimize V_(off), C_(it), A₀, A_(gs), while computing the parameters μ₀, U_(a) and U_(b) from the F₀G₀B₀T₀ characteristic. The data used are the 3 long channel gate characteristics with zero back-bias i.e., F₀G₀B₀T₀, F₀G₁B₀T₀ & F₀G₂B₀T₀.

For each trial set of V_(off), C_(it), A₀ & A_(gs) the mobility parameters μ₀, U_(a) and U_(b) are computed prior to computing the error used by the LMA. Now of these 7 parameters that were optimized C_(it) & A₀ will be updated in subsequent optimization steps but the other 5 parameters are at their final values. Store SC_(it)=C_(it).

Now we use the LMA to optimize U_(c), N_(factor), K₁, K₂, K_(eta), A₀. The parameter C_(it) is corrected. The data points used are all the gate characteristics for the FET #0 i.e., F₀G₀B₀T₀, F₀G₁B₀T₀, F₀G₂B₀T₀, F₀G₀B₁T₀, F₀G₁B₁T₀, F₀G₂B₁T₀, F₀G₀B₂T₀, F₀G₁B₂T₀ and F₀G₂B₂T₀. C_(it) is corrected in each iteration of the LMA, prior to computing the error used by the LMA, using the equation 11, where SC_(it) is the stored value of C_(it) at the end of Step 4. $\begin{matrix} {C_{it} = {{SC}_{it} - {N_{factor}\sqrt{\frac{q \cdot \varepsilon_{si} \cdot N_{ch}}{2 \cdot \phi_{s}}}}}} & (11) \end{matrix}$

Now store for future use, GC_(it)=C_(it) and the long-channel threshold voltage GV_(th)=V_(th).

Next, temporary reference values of the parameters D_(VT0) & C_(dsc) are obtained which will be used in the next step. No correction needs to be made because these values of D_(VT0) & C_(dsc) are only temporary. First set D_(VT1)=0.02, which will activate D_(VT0) & C_(dsc). D_(VT2) is already zero.

Now the LMA is used to optimize the parameters D_(VT0) & C_(dse) using the sub-threshold region of the curve F₃G₀B₀T₀, so that the V_(th) and the sub-threshold swing is adjusted. At this point you have a combination of D_(VT0), D_(VT1) & C_(dse) which fits the sub-threshold region of the shortest channel device and also you know that if D_(VT0) & C_(dsc) are zero, the sub-threshold region of the longest channel device is fitted.

Store the values MC_(it)=C_(it) and MC_(dsc)=C_(dsc). A common reference bias point B_(ref) is chosen on the gate curves F₀G₀B₀T₀, F₁G₀B₀T₀, F₂G₀B₀T₀ & F₃G₀B₀T₀ which has a V_(gs) slightly above threshold, zero V_(bs) and the minimum V_(ds). This B_(ref) is our reference for the corrections. Now at B_(ref) the following reference values are recorded for FET #3 from the length correction term in the V_(th) eqn in the BSIM3 model. Also store the V_(th) obtained as V_(th) _(—) _(SC). $\begin{matrix} {Q_{SC} = {P\left( {1 + \left( {2 \cdot P} \right)} \right)}} & (12) \\ {P = {\mathbb{e}}^{\frac{{- D_{{VT}\quad 1}} \cdot L_{eff}}{2 \cdot l_{t}}}} & (13) \\ {T_{1{\_ SC}} = {{K_{1{ox}}\left( {\sqrt{1 + \frac{N_{lx}}{L_{eff}}} - 1} \right)}\sqrt{\phi_{s}}}} & (14) \end{matrix}$

Similarly bias the FET #0 at B_(ref) and store the corresponding values of Q_(LC), T₁ _(—) _(LC) and V_(th) _(—) _(LC). LC stands for long-channel and SC stands for short-channel

Upto here we only considered the long-channel or short-channel devices one at at time. Now we consider all four devices FET #0, FET #1, FET #2 & FET #3, optimizing D_(VT1) & and N_(1x)while correcting the parameters C_(dsc), C_(it) & D_(VT0). The data to optimize on is the sub-threshold region of the curves F₀G₀B₀T₀, F₁G₀B₀T₀, F₂G₀B₀T₀ & F₃G₀B₀TO₀. First perform the corrections given by equations 15, 16 & and 17. $\begin{matrix} {C_{dsc} = \frac{{MC}_{it} + \left( {{MC}_{dsc} \cdot Q_{SC}} \right) - {GC}_{it}}{Q_{SC} - Q_{LC}}} & (15) \\ {C_{it} = {{GC}_{it} - \left( {C_{dsc} \cdot Q_{LC}} \right)}} & (16) \\ {D_{{VT}\quad 0} = \frac{V_{th\_ SC} - T_{1{\_ SC}} - V_{th\_ LC} + T_{1{\_ LC}}}{\left( {Q_{LC} - Q_{SC}} \right)\left( {V_{bi} - \phi_{s}} \right)}} & (17) \end{matrix}$

In order to keep the fit of the long channel accurate, after these corrections are performed, using these new values correct the base V_(th0) using the equation 18 before computing the error in each LMA iteration. The value of P is the same as in the equation 13. $\begin{matrix} {V_{{th}\quad 0} = {{GV}_{{th}\quad 0} - T_{1{\_ LC}} + \Delta_{vth}}} & (18) \\ {T_{1{\_ LC}} = {{K_{1{ox}}\left( {\sqrt{1 + \frac{N_{lx}}{L_{eff}}} - 1} \right)}\sqrt{\phi_{s}}}} & (19) \\ {\Delta_{vth} = {{D_{{VT}\quad 0} \cdot {P\left( {1 + \left( {2 \cdot P} \right)} \right)}}\left( {V_{bi} - \phi_{s}} \right)}} & (20) \end{matrix}$

So in this optimization step the long channel device FET #0 is unaffected, the sub-threshold slope and the V_(th) of the short-channel devices FETs #1, #2 & #3 are optimized.

Now we fit the high V_(ds) short channel behavior. The data used is the sub-threshold region of the highest V_(ds) gate curve F₃G₂B₀T₀. The parameter D_(sub)=0.02 for this step. No corrections are made. The parameters optimized are P_(dibl2), P_(clm), A₂, Eta₀, V_(sat) & C_(dscd).

Next the entire curve F₃G₂B₀T₀ is optimized for the parameters R_(dsw), P_(rwg), A₂, P_(vag), V_(sat) & A₁.

Finally all three short channel gate curves F₃G₀B₀T₀, F₃G₁B₀T₀ & F₃G₂B₀T₀ are optimized for the parameters R_(dsw), P_(dibl2), P_(clm), A₂, Eta₀, V_(sat), C_(dscd), P_(rwg), P_(vag) & A₁. No corrections are made. In all three steps above we only use the curves with V_(bs)=0, because no back-bias parameters are being fitted.

In the previous step the shortest channel gate curves were optimized with D_(sub)=0.02. Now the gate characteristics of the devices FET #1 & #2 are optimized while P_(dibl1) & and Eta₀ are corrected, so as to keep the fit of the FET #0 the same. The parameters fitted are P_(dibl2), D_(rout) & D_(sub). The data used are all the gate curves for FET #0, #1 & #2, with V_(bs)=0. The initial values of P_(dibl2) and Eta₀ are stored in SP_(dibl2) & SEta₀ respectively. We also store the value of T given by the equation 21 as ST. $\begin{matrix} {T = {P_{1}\left( {1 + \left( {2 \cdot P_{1}} \right)} \right)}} & (21) \\ {P_{1} = {\mathbb{e}}^{\frac{{- D_{sub}} \cdot L_{eff}}{2 \cdot l_{t}}}} & (22) \end{matrix}$

Next a common reference bias point B_(ref) is chosen with zero V_(bs), and a V_(gs) & V_(ds) above V_(th0). This is used to make the corrections. For each set of trial values of P_(dibl2), D_(rout) & D_(sub), obtain the initial value of T of equations 21, 22 & θ_(rout) of equations 23, 24 and then the corrections performed before computing the error in each LMA iteration are the equations 25, 26. $\begin{matrix} {\theta_{rout} = {{P_{{dibl}\quad 1} \cdot {P_{2}\left( {1 + \left( {2 \cdot P_{2}} \right)} \right)}} + P_{{dibl}\quad 2}}} & (23) \\ {P_{2} = {\mathbb{e}}^{\frac{{- D_{rout}} \cdot L_{eff}}{2 \cdot l_{t}}}} & (24) \\ {P_{{dibl}\quad 1} = \frac{{SP}_{{dibl}\quad 2} - P_{{dibl}\quad 2}}{\theta_{rout}}} & (25) \\ {{Eta}_{0} = \frac{{SEta}_{0} \cdot {ST}}{T}} & (26) \end{matrix}$

Now the back bias dependence of the V_(th) and the subthreshold swing at short gate length is fitted. The parameters C_(dscb) & Eta_(b) are optimized using the subthreshold region of the short channel gate characteristics F₃G₂B₂T₀ & F₃G₀B₂T₀. No corrections are made.

Now the parameter K_(T1) is optimized and the parameters μ_(te), U_(a1) & U_(b1) are computed. The data used is the long channel low V_(ds) gate characteristic with zero V_(bs) at high temperature F₀G₀B₀T₁.

For each value of K_(T1), compute the required mobility M μ₀, MU_(a) & MU_(b) from the F₀G₀B₀T₁ characteristic using the mobility computation method. Then compute the parameters μ_(te), U_(a1) & U_(b1) from the equations 27, 28 & 29 respectively. $\begin{matrix} {\mu_{te} = \frac{\ln\left\lbrack {{M\mu}_{0}/\mu_{0}} \right\rbrack}{\ln\left\lbrack {T_{hot}/T_{cold}} \right\rbrack}} & (27) \\ {U_{a\quad 1} = \frac{{MU}_{a} - U_{a}}{\left\lbrack {T_{hot}/T_{cold}} \right\rbrack - 1}} & (28) \\ {U_{b\quad 1} = \frac{{MU}_{b} - U_{b}}{\left\lbrack {T_{hot}/T_{cold}} \right\rbrack - 1}} & (29) \end{matrix}$

The error is computed at each step and the combination of K_(T1), μ_(te), U_(a1) & U_(b1) giving the least error is chosen.

Now the parameters K_(T2) and & U_(c1) are optimized using the F₀G₀B₂T₁ long channel gate characteristic at low V_(ds), high V_(bs) and high temperature. This optimizes the V_(th) and mobility dependence on back-bias at high temperatures.

Next the parameter K_(T1l) is optimized using the sub-threshold region of the F₀G₀B₀T₁, F₁G₀B₀T₁, F₂G₀B₀T₁ & F₃G₀B₀T₁ gate characteristics.

Now the change in saturation velocity and source/drain resistance with increase in temperature is fitted. So the parameters A_(T) & P_(rt) are optimized using the high V_(ds), zero V_(bs), high temperature long channel gate characteristic F₀G₂B₀T₁.

Now the narrow-width effect is fitted by the LMA using the device FET #4. The parameters to be optimized are K₃ & W₀. Start by storing the value of V_(th0) at the beginning of this step as the variable GV_(th0). Since the correction to V_(th) that we make for the narrow width FET #4, will also affect the V_(th) of the devices FET #0, #1, #2 & #3 which have already been optimized, a correction to the V_(th0) will have to be performed. $\begin{matrix} {V_{{th}\quad 0} = {{GV}_{{th}\quad 0} - \frac{K_{3} \cdot T_{ox} \cdot \phi_{s}}{W_{eff\_ LC} + W_{0}}}} & (30) \end{matrix}$

The data to be optimized to is the gate characteristic F₄G₀B₀T₀. For each trial set of K₃ & W₀, correct the value of V_(th0) using the equation 30, where W_(eff) _(—) _(LC) is the W_(eff) of the long channel device, before computing the error in the LMA. In this way the V_(th) of the devices FET #0, #1, #2 & #3 are unaffected by the new values of K₃ & W₀.

Now the back-bias dependence of the narrow-width effect is fitted by the LMA using the device FET #4. Start by storing the value of K₂ at the beginning of this step as the variable GK₂. $\begin{matrix} {K_{2} = {{GK}_{2} + \frac{K_{3\quad b} \cdot T_{ox} \cdot \phi_{s}}{W_{eff\_ LC} + W_{0}}}} & (31) \end{matrix}$

The data to be optimized to is the gate characteristic F₄G₀B₂T₀. The parameter optimized is K_(3b). For each trial value of K_(3b) correct the value of K₂ using the equation 31, where W_(eff) _(—) _(LC) is the W_(eff) of the long channel device, before computing the error in the LMA.

Now the reverse narrow-width effect is fitted. The parameters D_(VT0w), D_(VT1w) & D_(VT2w) are optitized using the LMA. The data points used are the low V_(ds) gate characteristics F₀G₀B₀T₀, F₀G₀B₁T₀, F₀G₀B₂T₀, F₃G₀B₀T₀, F₃G₀B₁T₀, F₃G₀B₂T₀, F₄G₀B₀T₀, F₄G₀B₁T₀, F₄G₀B₂T₀, F₅G₀B₀T₀, F₅G₀B₁T₀ & F₅G₀B₂T₀. It is important to set an upper limit to the parameter D_(VT1w). 

1. A method for determining compact model parameters for test devices in an integrated circuit chip comprising the steps of: measuring the electrical characteristics of one or more test devices in a fabricated integrated circuit, selecting a subset G of the electrical characteristics to optimize, selecting an initial set K of model parameters to optimize, setting the values of the remaining set P of model parameters so as to minimize or nullify their effect on the characteristics yielded by the model, optimizing the set K of parameters in order that the model yields characteristics whose numerical value best approximates the subset G of the electrical characteristics for the test devices, storing the optimized values of the set K of parameters as the data Q. storing the obtained values of variables used inside the compact model as the data F, further selecting a set M of model parameters from the set P of model parameters, to optimize, further selecting a subset R of the electrical characteristics to optimize, optimizing the set M of parameters in order that the model yields characteristics whose numerical value best approximates the subset R of electrical characteristics, while simultaneously adjusting the values of the set K of parameters based on the characteristics G and the values used in the optimization, of the set M of model parameters.
 2. The method of claim 1 where the the electrical characteristics of the test devices are not measured but instead are mathematically generated.
 3. The method of claim 1 further including the use of the data Q in computing the adjustment made to the values of the set K of parameters when optimizing the set M of parameters.
 4. The method of claim 1 further including the use of the data F in computing the adjustment made to the values of the set K of parameters when optimizing the set M of parameters.
 5. The method of claim 1 where the adjustment made to the values of the set K of parameters when optimizing the set M of parameters is performed in a manner that the effect of the 5 adjustment, on the characteristics yielded by the model counteracts the effect of the optimized values of the set M of parameters, on the characteristics yielded by the model.
 6. The method of claim 1 where the adjustment made to the values of the set K of parameters when optimizing the set M of parameters is computed from a mathematical relationship between the members of the set K of parameters and the members of the set M of parameters when the model is biased at the same operating point used in the subset G of the electrical characteristics for the test devices.
 7. The method of claim 1 where the adjustment made to the values of the set K of parameters when optimizing the set M of parameters is computed from a mathematical relationship between the members of the set K of parameters and the members of the set M of parameters when certain variables used inside the compact model are maintained at their value in the data F.
 8. The method of claim 3 where the the electrical characteristics of the test devices are not measured but instead are mathematically generated.
 9. The method of claim 4 where the the electrical characteristics of the test devices are not measured but instead are mathematically generated.
 10. The method of claim 5 where the the electrical characteristics of the test devices are not measured but instead are mathematically generated.
 11. The method of claim 6 where the the electrical characteristics of the test devices are not measured but instead are mathematically generated.
 12. The method of claim 7 where the the electrical characteristics of the test devices are not measured but instead are mathematically generated. 